In memories input buffers are required for address signals, data signals, and control signals such as a chip enable signal or a write enable signal. In these applications it is generally desirable for the input buffer to have high speed and low power. More subtle considerations include noise immunity and address float. Address float occurs when the input address is allowed to be simply high impedance so that the input voltage is not driven to any particular state but is allowed to "float." Although particularly common for addresses, this can be true for other signals as well. Outputs of microprocessors which provide the address signals are commonly tri-stated between active cycles. It is desirable that the input buffer not cause problems internal to the memory in this type of case. One thing that is desired is for the memory to not respond to a floating address as numerous transitions. In many memories, particularly static random access memories (SRAMs), the memory is designed to respond to address transitions. In such a memory most of the power consumption is in response to an address transition. Accordingly, it is desirable that during address float, which may result in any D.C. input voltage, that the address buffer not oscillate back and forth between two logic states. Additionally, for slow address transitions there may be a small amplitude, high frequency signal superimposed on the slow moving input signal. In such case there can be a response back and forth to the high frequency signal when the input signal is near the switch point of the input buffer. These problems have been addressed by providing hysteresis to change the switch point after the switch point has been initially reached. Although hysteresis has been useful in dealing with the problems of a floating or slow moving input, adding hysteresis has also resulted in reduced speed and/or increased circuit complexity with the consequent chip area penalty. Another problem with address float and the accompanying D.C. voltage level which can foreseeably be anywhere between the power supply voltages (voltages outside the power supply voltages present problems more associated with input protection than signal interpretation), is that the address may be interpreted as being a logic high for some portions of the internal circuit while interpreted as a logic low for some other portions. This can have the undesirable result of selecting two decoders which are intended to be exclusive of each other. Another criterion, for typical SRAM applications, is that the address buffer must be able to conveniently provide signals needed for address transition detection.